A to Z Platforms for Electronics Engineers
16-Bit RISC Processor Design
High-Performance 16-Bit MIPS Processor Design
Verilog-Based RISC-V Processor Implementation
32-Bit 5-Stage Pipelined MIPS Processor Implementation
High-Performance 32-Bit RISC-V Processor: RTL to GDS Flow
Verilog-Based Asynchronous Processor Design
Low Power DNN Accelerator with Mean Error Minimized....
High-Efficiency Squarer Circuit Design
Optimized Braun Multiplier IP Core
Efficient Baugh-Wooley Multiplier IP Core
High-Performance Booth Multiplier IP Core
Optimized Dadda Multiplier IP Core
High-Efficiency Vedic Multiplier IP Core
High-Efficiency Wallace Tree Multiplier IP Core
High-Speed Arithmetic Logic Unit (ALU) Design
Scalable Low Power 4-Bit Hybrid Full Adder for Fast Computation
Energy-Efficient 4-Bit Vedic Multiplier using Modified GDI
Ultra Low Power Approximate 4-2 Compressor
Design of Ultra Low Power Multipliers with Approximate 4-2 Compressors
Design of a Scalable Low Power Ripple Carry Adder for Fast Computation
