A to Z Platforms for Electronics Engineers
Unsigned 8-bit Restoring Divider using Vivado
Optimized AXI Interconnect IP Core Design
Optimized APB Interconnect IP Core
Efficient AXI-to-APB Bridge IP Core
Efficient AHB-to-APB Bridge IP Core
Verilog-Based UART Protocol Implementation
Verilog-Based SPI Protocol Implementation
Verilog-Based I2C Protocol Implementation
Verilog-Based Cyclic Redundancy Check (CRC) Implementation
1x3 Router Design and Implementation
FPGA-Based SDRAM Controller Design
Verilog-Based Synchronous FIFO Design and Verification
Verilog-Based Asynchronous FIFO Design and Verification
Low-Power Methodologies for Asynchronous FIFO Design and Implementation
Design of Low Power SRAM Cells with Increased Read/Write Performance
Inverter Design and Analysis Using Cadence Virtuoso
Inverter Design and Analysis Using Open-Source Tools
Logic Gate Schematic and Layout Design in Cadence Virtuoso
Differential Amplifier Design in Cadence Virtuoso
Operational Amplifier Design in Cadence Virtuoso
