The multiplexer (MUX) is an outstanding, all-rounder, and one of the most widely used circuits in digital design. Multiplexer comes under the category of combinational #circuits. Combinational Logic Circuits as the name propose consisting of a combination of #logicgates whose output at any instant of time is determined by the present combination of inputs only. Combinational circuits, therefore, are also called a memoryless system as the output is only dependent on the present values of input. This article covers a complete discussion on multiplexers, demultiplexers, their types, functions, and applications.

**What is Multiplexer(MUX)?**

**A mux is a** many to one circuit, which means it selects #binary information from one of many inputs lines and gives an output. The selection of a particular input is controlled by a particular set of select lines. There are n select lines for 2^n input lines.

For m number of total input lines and n number of select lines, the general block diagram of a multiplexer is as below.

**What are the Types of Multiplexer?**

There are various **types of multiplexers. **Some of them are 2:1 MUX, 4:1 MUX, 8:1 MUX, and so on. Where 2,4,8,16 indicate the input line and 1 indicate the output line.

A 2:1 MUX consists of the following elements, two input lines I(0) and I(1), one data select line named S, and an output line namely Y. The output of a 2:1 MUX is **Y=S'I(0)+SI(1)**. This implies when the select line is at zero(0) then the output y will show the data present in the I(0) input line and when the select line is at one(1) the data on the I(1) input line will be produced at the output. A 2:1 MUX is the simplest type of MUX. The internal structure of a 2:1 MUX consist of AND gate, OR gate, and NOT gate.

Similarly, a 4:1 MUX contains 4 input lines, two select lines, and a single output line. The output of a 4:1 MUX is;

**Y= S'(1)S'(0)I(0)+S'(1)S(0)I(1) + S(1)S'(0)I(2) +S(1)S(0)I(3)**

Let's understand how the output of a 4:1 MUX is obtained. From the **mux truth table**, it can be understood that for a binary zero in the select lines I(0) is selected at the output, similarly for a binary one I(1), for binary two I(2), and for binary three I(3) is presented at the output.

**How to ****implement**** a ****higher-order**** MUX using a lower order MUX?**

It is interesting to recognize how a higher-order multiplexer can be implemented using a lower order multiplexer. Let's understand this concept with an example. Implementation of 4:1 MUX by 2:1 MUX. This is quite an easy process to implement.

**4/2=2 MUX=>2/2= 1 MUX**

**Total = 2+1=3 (2:1MUX)**

Similarly 64:1 MUX by 4:1

**64/4=16 MUX=>16/4=4 MUX =>4/4= 1 MUX**

**Total= 16+4+1=21 (4:1MUX).**

In this, any higher-order multiplexer can be implemented using a lower order multiplexer.

Note:- For the implementation of **2^n:1** MUX using 2:1 MUX, a total of 2:1 MUX required is

**(2^n -1)**

**MUX as a Universal Logic gate**

A multiplexer is also utilized as a universal logic converter because it can execute all standard logic gates. The figure below represents the various logic gate using a multiplexer. Basic gates implementation requires a single 2:1 MUX, whereas the universal and special purpose gates require 2, 2:1 MUX.

### Application of MUX

A multiplexer sees various applications in the digital system, few of them are as #universal logic converter, data selector, many to one circuit, parallel to serial converter as well as a waveform generator.

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Using

Using a 4:1 MUX and a NOT gate, all two-variable functions along with all three variable functions can be realized.

Using

Using a 4:1 MUX and a NOT gate, all three-variable functions, along with all four variable functions can be realized.

A minimum of 3, 2:1 MUX is required to implement a half adder or a half subtractor.

**What is a Demultiplexer (DEMUX)?**

**DEMUX **(or Demultiplexer) **is a combinational circuit **that has a single input data line and multiple output data lines. As the name signifies a demultiplexer works exactly opposite to a multiplexer. Generally, there are n select lines for 2^n output lines. A DEMUX is not used as a universal gate. A DEMUX contains #AND gates. A common image of a demultiplexer is shown in the figure. The total number of output lines is denoted by **m=2^n **for** 'n'** number of select lines.

__What are the types of Demultiplexers or DEMUX?__

__What are the types of Demultiplexers or DEMUX?__

Similar to MUX, there are also various types of Demux, 1:2 DEMUX, 1:4 DEMUX, 1:8 DEMUX, and so on. Where 2.4,8,16 indicates output lines and 1 indicates an input line. Let us learn the functioning of a DEMUX by taking the example of 1:2 DEMUX.

The block diagram is as shown, it constitutes a single input line **I**, two output lines **Y(0)**, and **Y(1)**, and a select line **S**. The outputs obtained from the **demux truth table** are **Y(0)= S'I**, and **Y(1)= SI. **This implies when the select line is a binary zero, the input is related to the Y(0) output line. Similarly, when the select line is a binary one, the input is related to the Y(1) output line.

### Application of DEMUX

The application of Demux (or Demultiplexer) is as a data distributor, in serial to parallel conversion, as one to many circuits, used to perform the reverse operation of a MUX, etc.

__Some ____essential____ ____details____ of ____a Demultiplexer__

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__a Demultiplexer__

The decoder

A decoder with enable input works as a DEMUX.

The decoder is also composed of AND gates or NAND gates.

A 2x4 decoder can act like a 1:4 DEMUX and vice versa.

A brief idea about decoders, A Decoder is a combinational circuit with many inputs and many outputs. Some popular decoders are Binary to octal(3-8 line decoder), Binary to Hexadecimal(4-16 line decoder), BCD to Decimal, BCD to Seven segment display. If there are **n **number of total input lines then the total number of output lines is **2^n.**

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Brilliant explanation! Thanks, LearnElectronics India!