A to Z Platforms for Electronics Engineers
Verilog-Based I2C Protocol Implementation
Optimized Dadda Multiplier IP Core
Inverter Design and Analysis Using Cadence Virtuoso
1x3 Router Design and Implementation
Optimized Braun Multiplier IP Core
Verilog-Based Synchronous FIFO Design and Verification
Low-Power Methodologies for Asynchronous FIFO Design and Implementation
High-Performance 16-Bit MIPS Processor Design
Low Power DNN Accelerator with Mean Error Minimized....
High-Performance IIR Filter Design in Verilog
Optimized APB Interconnect IP Core
Unsigned 8-bit Restoring Divider using Vivado
High-Efficiency Vedic Multiplier IP Core
Verilog-Based RISC-V Processor Implementation
Design of a Scalable Low Power Ripple Carry Adder for Fast Computation
Efficient Baugh-Wooley Multiplier IP Core
Logic Gate Schematic and Layout Design in Cadence Virtuoso
Scalable Low Power 4-Bit Hybrid Full Adder for Fast Computation
Ultra Low Power Approximate 4-2 Compressor
Verilog-Based Asynchronous FIFO Design and Verification
High-Performance FIR Filter Design in Verilog
Motion Detection with Bluetooth-based alert using Spartan 6 EDGE board
LED Blinking & Pattern Generation Using Spartan 6 - Project
Smart Distance Measurement & Alert System Using Ultrasonic Sensor & Spartan 6
