• Dhanush kumar S

N-MOS, P-MOS & C-MOS Transistors

Updated: Dec 1, 2020

A transistor is nothing but a semiconductor device employed to switch or amplify electrical signals. It is manufactured from a semiconductor material normally with at least three terminals to establish a connection with any external circuit. Transistors represent a vital role in the development of small electronic devices such as calculators, radios, speedometers, and many other measuring devices. Transistors are of several types.

Bipolar Junction Transistor (BJT), Junction gate Field Effect Transistor (JFET), Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and many more. Apart from all the transistors, MOSFET is employed at most for its unique features. The MOSFET has been discussed already in the previous article and the link is shared below.

In this article, we are going to discuss in brief about the types of MOSFETs. They are N-MOS, P-MOS, and C-MOS #transistors.


  • The Negative-MOS transistor can be operated in both the enhancement as well as in the depletion mode.

  • The source and drain #terminals are heavily doped with donor ions such as arsenic or phosphorus (N-type).

  • The substrate is doped with a P-type semiconductor.

  • Drain #resistance is low when compared to the P-MOS transistor.

Enhancement mode N-MOS transistors

In enhancement mode N-MOS transistor, The drain current will flow only if the gate #voltage applied to the gate terminal is greater than the threshold voltage. This enables the conductance which makes it a transconductance #device. The application of positive gate voltage to an n-type MOSFET attracts more electrons towards the oxide layer thereby increasing the thickness of the channel allowing more current to flow. The minority carriers (holes) get repelled and the majority carriers (electrons) get attracted to the oxide layer.

The current flow gets improved due to the increase in electron flow better than in depletion mode.

Depletion mode N-MOS transistors

If the N-MOS has to be operated in the depletion mode, the gate terminal should be at negative potential while the drain terminal should be at the positive potential. In depletion N-MOS transistor, the negative source-gate voltage will deplete the conductive channel of its free electrons. So, the transistor gets switched OFF. In other words, more the positive gate-source voltage, more electrons that result in more current flow.

The minority carriers (holes) get attracted and settle near the oxide layer, whereas the majority carriers (electrons) gets repelled away. The channel which is present close to the drain gets depleted more when compared to the one present near the source.

P-MOS Transistor:

  • The source and drain terminals are heavily doped with acceptor ions such as boron (P-type).

  • The substrate is doped with an N-type semiconductor.

  • It possesses high drain resistance when compared to the N-MOS transistor.

  • Same as that of N-MOS transistor, the Positive-MOS transistor can also be operated in both enhancement as well as in the depletion mode

  • A thin layer of Silicon oxide is grown over the surface.

Enhancement mode P-MOS transistors

By the application of a negative gate voltage to the gate terminal, the conductivity of the channel gets enhanced. Due to the presence of a positive region, the hole #current is increased through the diffused P-channel, thus making the P-MOS work in the enhancement mode. Thus whenever there is no gate-source voltage, the device is in the "OFF" state and the channel gets open.

Depletion mode P-MOS transistors

The application of a positive gate voltage to the gate terminal results in the repulsion of majority carriers (holes). Because of this, a depletion layer gets formed and the flow of current is reduced. This reduction in the flow of current makes the P-MOS to work in the depletion mode. Thus, the positive gate-source voltage turns the depletion P-MOS transistor "OFF" and the negative gate-source voltage turns "On" the transistor.

The following table will explain the comparison of voltage involved in the functioning of N-MOS and P-MOS transistors.

Complementary (C-MOS) transistor

C-MOS or the Complementary MOS transistor was developed in 1963 by Chih tang and Frank Wanlass. This logic uses both N-MOS and P-MOS transistors which are connected in a push-pull arrangement. The main reason behind the introduction of C-MOS transistors is because of the overheating of ICs caused by densely packed transistors in a smaller area.

In C-MOS logic, both the gates of N-MOS and P-MOS transistors are connected together. The source of P-MOS is connected to the positive drain voltage and the N-MOS is connected to the negative drain voltage. similarly, the drain terminals of both transistors are also connected together.

When the input is kept low (0 volts), the gate of one MOSFET will be "ON" but the other one will be at "OFF". As a result of this configuration, both #resistances of MOSFETs will act as a potential divider and the output will be approximately equal to the drain voltage.

when high voltage flows through the circuit, the gates of N-MOS transistors conduct and P-MOS won't conduct. In this case, the output will be 0 volts. This gives sufficient switching time as the voltage flows from one state to another. The power consumption of the C-MOS transistor is zero, whenever DC voltage is used.

The main advantage of C-MOS transistors is the low power dissipation which is equal to 50nW. The C-MOS gates can be easily constructed and the output of C-MOS is pretty much rail-to-rail. They also possess high input impedance and so the resistance of them is virtually infinite.

See also:

  1. MOSFET Transistor

  2. Design flow of VLSI Technology

  3. What is VLSI Technology?

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